The industry drive toward smaller size packages for integrated circuits is driving the adoption of 3D stacking of dies with TSV (Through Silicon Via, sometimes Through Substrate Via) connections as well as wafer level packaging of devices. These technologies will become increasingly advantageous in the field of CMOS image sensors.
In a conventional fabrication process, an active device wafer including, for example, CMOS image sensors devices, is provided. Color filter array (CFA) and microlens (ML) materials may be formed over the CMOS image sensors. The CFA and ML material is disposed in locations corresponding to photodiodes in the CMOS image sensors so that impinging light may be directed onto the photodiodes.
A glass substrate may be bonded over the active device wafer and over the photodiodes. On an opposing surface of the structure, a through via process such as TSV may be performed to open vias to metallization layers. An isolation oxide may be formed in the through vias. A conductor material may be deposited in the through vias and may extend to the metallization layers to form an electrical connection to the CMOS image sensor devices. A redistribution layer (RDL) may be formed over the through vias and patterned to form traces. External connectors may be formed on the traces to complete a package for the CMOS image sensor devices. A sawing or dicing operation may then separate the active device wafer, the glass substrate, into individual integrated circuit modules each forming CMOS image sensor devices for use in a system.
Traditional CIS devices involve limitations, such as (1) the top glass layer, used in manufacturing the device, reduces the optical performance; and (2) the CTE (Coefficient of Thermal Expansion) mismatch between, e.g., the active device wafer upon which the device is formed, and, e.g., a glass substrate used for manufacturing, induces wafer warping and bowing, resulting in performance non-uniformity and reliability concerns.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale.